Linux Hardware Compatibility HOWTO
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# 4. CPU/FPU

Please see this note for more on non-x86 hardware.

## 4.1. Intel

Intel 386SX/DX/SL, 486SX/DX/SL/SX2/DX2/DX4, Pentium, Pentium Pro, Pentium II, Pentium III (regular and Xeon versions), Pentium 4, and Celeron (including mobile versions of all of the above) are all supported.

## 4.2. AMD

AMD 386SX/DX, 486SX/DX/DX2/DX4, K5, K6, K6-2, K6-3, and Athlon (all varieties, including MP) are all supported. Older versions of K6 should be avoided as they are buggy. Setting "internal cache" disabled in bios setup can be a workaround. Some early K6-2 300Mhz have problems with the system chips.

AMD's 64-bit Opteron and Athlon64 processors, as well as the mobile Athlon64 (or Turion64), are also supported, running either in 32-bit or 64-bit mode. For 32-bit mode, compile a kernel for i386, optionally optimized for Athlons, since that's essentially what these processors look like in 32-bit mode. For 64-bit mode, compile a kernel for x86_64. It will still run 32-bit binaries, assuming all the appropriate libraries are available. Opteron and Athlon64 systems use standard PC hardware, so the information in this HOWTO still applies.

The old NexGen processors are also supported.

A few very early AMD 486DX's may hang in some special situations. All current chips should be okay and getting a chip swap for old CPU's should not be a problem.

## 4.3. Cyrix

Cyrix 386SX/DX, 486SX/DX, 5x86, 6x86, and MediaGX are all supported.

- enable cache on Cyrix processors

- Cyrix software cache control

- Cyrix 5x86 CPU register settings

## 4.4. IDT

IDT Winchip C6-PSME2006A processors are supported under Linux.

## 4.5. Transmeta

The Transmeta Crusoe processors are supported.

## 4.6. Misc. notes

Linux has built-in FPU emulation if you don't have a math coprocessor.

Linux supports SMP (multiple CPUs) in all 2.x kernels. See the Linux SMP HOWTO for more information.

ULSI Math*Co series has a bug in the FSAVE and FRSTOR instructions that causes problems with all protected mode operating systems. Some older IIT and Cyrix chips may also have this problem.

There are problems with TLB flushing in UMC U5S chips in very old kernels. (1.1.x)

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